BEGIN:VCALENDAR VERSION:2.0 PRODID:-//jEvents 2.0 for Joomla//EN CALSCALE:GREGORIAN METHOD:PUBLISH BEGIN:VTIMEZONE TZID:America/Bahia END:VTIMEZONE BEGIN:VEVENT UID:7d0a61b3f782e629118ef0368fe4ae0a CATEGORIES:Eventos PESC (Palestras, Seminários, etc.) SUMMARY:Seminário: Vijaykrishnan Narayanan (Pennsylvania State University) DESCRIPTION;ENCODING=QUOTED-PRINTABLE:
Seminário: Accelerating Visual Analytics Across the Memory and Stor age Stack
Palestrante: Vijaykrishnan Narayanan
Moderador: Prof. Diego Leonel Cadette Dutra.
Dia 26/06 (segunda-feira), 10 horas, Sala H-324B.
Transmissão pelo Canal do PESC no Youtube.
Abstract:
Data analytics involves the discovery o f patterns and com plex relations in data to assist with effective decision -making. Such analytics are applied on a variety of data forms such as vide o streams, financial data, social media messages, and sensor information fr om smart homes and personal health monitoring devices. However, data analyt ics is becoming exceedingly challenging as the generated volume of data is increasing exponentially. Co-design across the stack from materials to arch itectures will be vital to addressing cross cutting challenges posed by the enormity of data that needs to be processed. This talk will showcase such optimization targeted at visual analytic applications such as Deep Neural n etworks, graph analytics and query support.
First, I will present a Look-Up Table (LUT) based Pro cessing-In-Memory (PIM) technique with the potential for running Neural Net work inference tasks. The proposed LUT-based PIM methodology exploits subs tantial parallelism using look-up tables that preserve the bit-cell and per ipherals of the existing SRAM monolithic arrays in processor caches. Next, I will present GaaS-X, a graph analytics accelerator that inherently suppor ts sparse graph data representations using in-situ compute-enabled crossbar memory architectures. The proposed design alleviates the overheads of redu ndant writes, sparse to dense conversions, and redundant computations on th e invalid edges that are present in other state-of-the-art crossbar-based P IM accelerators. Finally, I will present an in-SSD key-value database that uses the embedded CPU core, and DRAM memory on the SSD to support various q ueries with predicates and reduce the data movement between SSD and host pr ocessor significantly.
Short Bio: p>
Vijaykrishnan Narayanan is the Associ ate Dean for Innovation in Engineering and A. Robert Noll Chair Professor o f Computer Science & Engineering and Electrical Engineering at the Pennsylv ania State University. Vijay received his Bachelors in Computer Science & E ngineering from University of Madras, India in 1993 and his Ph.D. in Comput er Science & Engineering from the University of South Florida, USA, in 1998 . He is a Fellow of the National Academy of Inventors, IEEE and ACM. He se rved as Editor-in-Chief of IEEE TCAD and ACM Journal of Emerging Technologi es in Computing Systems. He currently serves as Associate Editor-in-Chief o f IEEE Micro.
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